The invention relates to Field Programmable Gate Arrays (FPGAs). More particularly, the invention relates to structures for efficiently implementing large multiplexers in FPGAs.
Programmable logic devices (PLDs) are a well-known type of digital integrated circuit that can be programmed to perform specified logic functions. One type of PLD, the field programmable gate array (FPGA), typically includes an array of configurable logic blocks (CLBs) surrounded by a ring of programmable input/output blocks (IOBs). The CLBs and IOBs are interconnected by a general interconnect structure. Some FPGAs also include additional logic blocks with special purposes (e.g., DLLS, RAM, and so forth).
The general interconnect structure, CLBs, IOBs, and other logic blocks are typically programmed by loading a stream of configuration data (bitstream) into internal configuration memory cells that define how the programmable elements are configured. The configuration data may be read from memory (e.g., an external PROM) or written into the FPGA by an external device. The collective states of the individual memory cells then determine the functionality of the FPGA.
Efficient use of FPGA resources is important, because such efficiency can allow a user design to fit into a smaller (and less expensive) FPGA. For some very large designs, inefficient resource usage can result in an implementation so large it cannot be implemented in any FPGA available from a given FPGA provider. Therefore, an FPGA that can more efficiently implement common user functions provides a marketing advantage over its competitors. Hence, efficient FPGA implementations of common functions are highly desirable.
One function often used in user designs is the multiplexing function. A user defines a circuit to be implemented in the FPGA using either schematic entry, where components are explicitly identified for placement in the design, or in a high-level design language (HDL), where the behavior of the circuit is described and synthesis software is used to identify components to be used in the circuit implementation. Regardless of which method is used to specify the design, the resulting circuit implementation is likely to include a large number of multiplexers.
Multiplexers are especially common in circuit netlists generated by synthesis software, and the use of synthesis software is increasing as user circuits increase in size. Therefore, an efficient multiplexer implementation is an increasingly desirable feature in an FPGA.
The invention provides novel structures for implementing wide multiplexers from user designs in FPGAS. Traditionally, wide multiplexers from user designs are implemented using common FPGA elements such as function generators and smaller dedicated multiplexers. On the other hand, existing input multiplexers (which provide data input signals to the function generators) are controlled solely by signals stored in configuration memory cells. Hence, the existing input multiplexers are not available to implement wide multiplexers controlled by user control signals. According to the invention, the input multiplexers providing the function generator data input signals are modified to function under control of user signals. Thus, the input multiplexers of the invention are much more flexible than traditional input multiplexers.
A first aspect of the invention provides an FPGA configurable logic block (CLB) that includes: first and second bypass input multiplexers providing bypass signals from an FPGA general interconnect structure; a function generator with data input terminals; and a first data input multiplexer that provides signals from the general interconnect structure to one of the data input terminals of the function generator. (The terms xe2x80x9cbypass input multiplexerxe2x80x9d and xe2x80x9cbypass multiplexerxe2x80x9d are used herein to describe input multiplexers driving bypass input signals to the CLB, i.e., data input signals bypassing the function generator data input terminals. For example, in a Virtex or Virtex-II FPGA a bypass input signal BX or BY can drive the flip-flop directly, without passing through the function generator.) The first data input multiplexer includes a decoder circuit and a second stage multiplexer. The decoder circuit decodes user signals provided by the first and second bypass input multiplexers and provides control signals to select terminals of the second stage multiplexer. As directed by these control signals, the second stage multiplexer selects one of several values from the general interconnect structure and provides it to the function generator input terminal.
In one embodiment, the first data input multiplexer includes third multiplexers in addition to the second stage multiplexer. The third multiplexers are controlled by configuration data stored in configuration memory cells, in a manner similar to that of presently known input multiplexers.
In another embodiment, the second stage multiplexer is implemented as a group of pass transistors gated by logic gates. In one embodiment, the logic gates are controlled by both configuration memory cells and the control signals from the decoder circuit.
The data input multiplexer of the invention can be used on one, two, or more of the data input signals to the function generator. In one embodiment, the improved data input multiplexer is provided on two of four data input terminals of the function generator. In another embodiment, each data input terminal of the function generator uses an improved data input multiplexer according to the invention.
A second aspect of the invention provides a multiplexing input structure in an FPGA. The multiplexing input structure includes a first multiplexing circuit having data input terminals receiving user signals from the general interconnect structure, a select terminal receiving a bypass input signal also from the general interconnect structure, and an output terminal that drives one of the data input terminals of a CLB function generator.
In another embodiment, the multiplexing input structure includes second multiplexing circuits in addition to the first multiplexing circuit. The second multiplexing circuits are controlled by configuration data stored in configuration memory cells.
In another embodiment, the first multiplexing circuit is implemented as a group of pass transistors gated by logic gates. In one embodiment, the logic gates are controlled by both memory cells and the control signals from the decoder circuit.
According to a third aspect of the invention, an interconnect multiplexing circuit is provided that can be used to drive signal lines in the general interconnect structure. The interconnect multiplexing circuit of the invention extends the concept of mixed memory cell and user control of a multiplexer presented herein into the general interconnect structure of an FPGA.
According to one embodiment, the invention provides an interconnect multiplexing circuit that includes a first multiplexing structure having data input terminals coupled to receive signals from the general interconnect structure, a first select terminal receiving a signal from a signal line in the general interconnect structure, a second select terminal receiving a signal from a configuration memory cell, and an output terminal that drives one of the signal lines making up the general interconnect structure.